`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:06:36 12/11/2008 
// Design Name: 
// Module Name:    controller2 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module controller2(
    input clock,
    input reset,
    input [5:0] controllerIn,
	 output reg controller2Enable,
    output reg [15:0] controllerOut
    );
always@(posedge clock)
begin
	if(reset)
		controllerOut <= 16'd0;
	else
		begin
		controller2Enable <= 1;
		controllerOut[15:4] <= 12'd0;
		if(controllerIn[5] == 0)
		controllerOut[3:0] <= 4'h7;
		else if(controllerIn[4] == 0)
		controllerOut[3:0] <= 4'h8;
		else if(controllerIn[3] == 0)
		controllerOut[3:0] <= 4'h9;
		else if(controllerIn[2] == 0)
		controllerOut[3:0] <= 4'ha;
		else if(controllerIn[1] == 0)
		controllerOut[3:0] <= 4'hb;
		else if(controllerIn[0] == 0)
		controllerOut[3:0] <= 4'hc;
		else
		controllerOut[3:0] <= 4'h0;	
		controller2Enable <= 0;
		end
end

endmodule
